In integrated semiconductor memories, digital information items are stored in a multiplicity of memory cells that are in each case connected to a bit line and to a word line. Volatile semiconductor memories, in particular DRAMs (dynamic random access memory), possess memory cells that in each case have a selection transistor and a storage capacitor. The storage capacitor may be designed as a trench capacitor or as a stacked capacitor. One electrode of the storage capacitor can be electrically connected to a bit line by the selection transistor. By means of the bit line, a digital information item can be written to the storage capacitor or be read out from the latter. The transistor is electrically controlled by a word line. The transistor is often designed as a MOSFET (metal oxide semiconductor field effect transistor). Such a field effect transistor possesses a gate electrode, which simultaneously forms a section of the word line. The gate electrode is isolated from a channel region of the transistor by a dielectric layer, namely a gate oxide. A multiplicity of selection transistors are connected to each word line.
In present-day semiconductor memories, word lines usually have a master word line and a multiplicity of conductor segments connected to the master word line. The conductor segments are usually composed of polysilicon and form the gate electrodes of the selection transistors connected to the respective conductor segment. The same number of selection transistors is connected to each conductor segment of a word line. All the conductor segments of a word line are connected to the master word line. The master word line is usually composed of a metal and has a greater electrical conductivity than the conductor segments made of polysilicon. The metallic master word line serves for rapidly transmitting the control potentials for the word line to all the selection transistors connected to the word line. The control potentials for the word line are provided by at least one word line driver to which the word line is connected. The word line driver optionally provides a first or a second electrical potential for the word line. The word line is activated by the first electrical potential, as a result of which the selection transistors connected to the word line are opened. The word line is deactivated by the second electrical potential. The selection transistors connected to the word line are then closed.
Problems arise in integrated semiconductor memories if the electrical connection between a word line driver and the associated word line is interrupted on account of production-dictated faults. Causes of such electrical defects may be clipped, i.e., interrupted conductor connections in the metal plane in which the master word line is formed. A defect may equally be present in the polysilicon plane in which the conductor segments are produced. Furthermore, the connection between a master word line and a conductor segment may be interrupted, for example, due to a defective contact hole filling not effecting conductive connection. Particularly in the case of defective contact hole fillings, the cause is often due to the lithographic patterning of the contact holes. Thus, during the production of etching masks, lateral positional errors occur, which make it more difficult to effect a reliable electrically conductive connection of conductive structures deposited one on top of the other.
Therefore, before an integrated semiconductor memory is put into operation, an electrical functional test is carried out, during which selected memory addresses are written in and read out again in order to test proper operation of the memory. If a word line or a specific conductor segment of a word line is not conductively connected to a word line driver on account of a production fault, then the word line potential cannot be influenced in a targeted manner. The gate electrodes of the connected selection transistors then do not have a defined electrical potential, but rather are “floating,” that is to say that their electrical potential is determined by parasitic leakage currents in their surroundings and fluctuates unpredictably. The connected selection transistors cannot be opened or closed in a targeted manner, so that defective memory addresses and thus defective word lines or word line segments are easily identified during the electrical functional test.
In present-day semiconductor memories, defective word lines can be replaced by redundant word lines. In this case, the defective word line is electrically isolated from its word line driver with the aid of electrical fusible links. With the aid of so-called fuses and antifuses, redundant word lines can be driven as a replacement instead of the defective word lines.
However, the electrical effects of the disconnected floating word line continue to pose problems. Since the word line is no longer electrically connected to the word line driver, it can no longer be switched to the second electrical potential that would deactivate it. Consequently, selection transistors can be opened on account of parasitic leakage currents in the vicinity of the word line. As a result, the electrical charge stored in the associated storage capacitor flows onto a bit line and alters the bit line potential thereof. If this takes place at a point in time at which another memory cell connected to the same bit line is being read, a read-out error arises. This read-out error arises even when the word line that drives the memory cell being read is intact. Consequently, even after the repair of a defective word line, i.e., after the latter has been replaced by a redundant word line, errors can still occur during the electrical functional test.
In present-day semiconductor memories, the risk of floating disconnected word lines is also increased by the fact that active drivers are provided at a plurality of locations on a word line. Thus, each conductor segment connected to a master word line is biased directly with the first or second electrical potential by an active driver that connects the conductor segment to the master word line. In an active driver, the connected conductor segment can optionally be biased with the first, activating electrical potential via a p-channel transistor or with the second, deactivating potential via an n-channel transistor, or vice versa. Once a conductor segment has been activated, it is deactivated again when the memory information has been read out. For this purpose, it is connected to the deactivating second electrical potential by the corresponding transistor of the active driver. However, if the transistor is defective, for example on account of a defective electrical contact, then the driver exclusively effects an activation of the conductor segment. Since the conductor segment can no longer be deactivated, after the first potential has been switched off, the floating potential of the conductor segment is still higher than in the case of a semiconductor memory without an active word line driver at the conductor segment. The probability of read-out errors is additionally increased as a result.
German Patent Application 101 03 526 A1, which is incorporated herein by reference, discloses a semiconductor memory whose word line segments are locally activated and deactivated by transistors serving as electrical switches. However, the transistors used as switches do not prevent floating of word line segments whose driver-side end is electrically decoupled on account of a defect.